Every improvement project—whether a production line upgrade or an enterprise-wide digital rollout—faces two constant threats: hidden risks and unexpected costs. Change Flow Thinking (CFT) offers a clear, visual way to reveal those threats before they derail your plans. By mapping every decision, resource, and risk on a single tree-flow diagram, teams gain the confidence to push bold ideas forward without gambling on the outcome.
CFT shines whenever the path forward feels murky:
If the cost of getting it wrong is high, Change Flow Thinking helps you get it right—fast.
Ready to experience the framework first-hand? Launch a Change Flow Thinking project in the PRIZ Playground—no credit card, no downloads. Build your first diagram, invite teammates, and follow the guided workflow that turns complex ideas into a low-risk reality.
Innovation stalls when teams drown in spreadsheets and conflicting assumptions. By visualizing the entire change flow, CFT replaces guesswork with clarity. Companies that embed Change Flow Thinking report:
When your people see exactly why each task matters—and how it impacts the big picture—momentum soars.
This project investigates how to increase the copper removal rate during Chemical Mechanical Planarization (CMP). Functional modeling revealed that increasing H₂O₂ alone is ineffective beyond an optimum level because rapid oxidation creates a thick, passivating Cu₂O/CuO layer that must be mechanically removed. The winning direction is to balance faster oxidation with stronger mechanical removal by optimizing pad speed, abrasive concentration, pressure, conditioning, and slurry transport.
Wet cleaning is widely used in microchip manufacturing. Single wafer equipment is working as follows. A wafer rotates, and chemistry is poured from a movable nozzle. Water rinsing is performed at the end of the process. Loading of a new batch of the chemistry resulted in excursion - a strongly increased amount of defects was observed on the wafer after the processing. The project is dedicated to the failure analysis and creation of innovative solutions.
Semiconductor devices are becoming more complex and expensive. But what exactly are we paying for when we buy a computer, cellphone, or any device containing a microchip? It’s not for radically new functions—the core components remain the same: transistors and interconnections. According to Moore’s law, transistors are getting smaller, with more interconnection layers added, making the manufacturing process longer and more costly. In reality, we’re paying for the inability of engineers to efficiently solve engineering challenges. This project leverages System Functional Modeling (SFM) to analyze the IC interconnection layer and Process Functional Modeling (PFM) to evaluate its manufacturing process. These analyses aim to deepen our understanding of both the device and the production process, generating innovative solutions for cost reduction and improved efficiency.
The process is related to microelectronics - microchip manufacturing. The purpose of the process is to create a SiO2 layer on the surface of a Si wafer. Equipment: Vertical furnace to heat the wafers in the Q2 atmosphere and perform oxidation on the wafer surface. Process: The oxidation occurs on the front side and on the back side of the wafer Requirements: Create a SiO2 thin layer with a certain thickness and low sigma - low standard deviation of the thickness between the wafers and within the wafer Failure: Wafers from the lower zone have higher thickness and significantly higher within wafer sigma (standard deviation of the thickness within the wafer)
This project presents an innovative engineering solution for improving the corrosion resistance of dental implants. The proposed concept utilizes multi-layer ceramic and oxide coatings to provide long-term protection against corrosion, wear, and harsh oral conditions. By maintaining inner protective layers even after the outer layer degrades, the design aims to extend implant lifetime, improve reliability, and reduce the risk of implant failure. This concept was developed as part of the Engineering Thinking course in the Materials Engineering program.
Flash heating of a wafer is widely used in microchip manufacturing. The purpose of the process is to prevent the diffusion of ions and atoms. During the flash process, a wafer breakage occurs. The project's purpose is to learn and understand the mechanism of the wafer breakage and propose the solutions to prevent the wafer breakage
This project showcases how functional modeling can drive innovation by analyzing and simulating various versions of a vacuum cleaner. By studying the functional model, you will experience firsthand how the Functional Modeling creative thinking tool helps identify opportunities for improvement and generate innovative ideas for the next generation of products. Through this example, you’ll learn how to dissect the functionality of a vacuum cleaner, revealing ways to enhance its performance, efficiency, and user experience—ultimately paving the way for future innovations.
Copper electroplating is essential for forming advanced semiconductor interconnects, yet radial thickness non-uniformity remains a costly challenge. Thicker deposition at the wafer edge and thinner copper at the center force manufacturers to rely on overplating and CMP compensation, increasing material waste and process cost. Using the PRIZ Platform, this project reveals that the true amplification mechanism lies in operating within a kinetically controlled regime, where small voltage variations caused by seed-layer resistance produce large thickness deviations. By shifting the process closer to diffusion-controlled behavior and reducing sensitivity to voltage fluctuations, uniform deposition can be achieved intrinsically — enabling thinner seed layers, reduced overplating, lower CMP burden, and overall cost reduction.
